搜索资源列表
FPGA-1553B
- MIL-STD一1553B是一种集中控制式、时分指令/响应型多路串行数据总线标 准，具有高可靠性和灵活性，已经成为现代航空机载系统设备互联的最有效的解 决方案，广泛的应用于飞机、舰船、坦克等武器平台上，并且越来越多的应用到 民用领域。完成1553B总线数据传输功能的关键部件是总线接口芯片11][41。 在对M几STD一1553B数据总线协议进行研究后，参考国外一些芯片的功能结 构，结合EDA技术，本论文提出了基于FPGA的1553B总线接口芯片的设计方案。 在介绍了总线控
m
- 四人抢答器，使用FPGA开发工具，可以在电脑上直接运行，但是要结合硬件使用
M序列发生器的FPGA实现
- M序列发生器的FPGA实现
目前以太网PHY芯片是通过总线MDC/MDIO
- 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理,At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA
FPGA_MP3.rar
- 该程序包为FPGA的例子，用FPGA来设计MP3播放器,The package for the FPGA example, using FPGA to design MP3 player
FPGA-DE1-PACMAN
- Pacman 4 DE1-FPGA-Board
LVDS_Serdes_list_FPGA1
- FPGA之间的LVDS传输，采用serdes接口，传输速率达到400m-LVDS transmission between the FPGA using serdes interface, transfer rate up to 400m
PitchMarker.m
- This the pitch marker to be used with the PSOLA algorithm for pitch shifting-This is the pitch marker to be used with the PSOLA algorithm for pitch shifting
m-mtip-10_100_1000_ethermac
- 10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.
Cyclone2_mp3
- NIOS下mp3解码程序，已验证通过，可以用来做FPGA的MP3解码器使用-NIOS Under the mp3 decoding process has been verified by, can be used to make the MP3 decoder using FPGA
crossroute-R4
- As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstalk has primarily been a concern for ASICs, multi-chip modules, and
FPGA-Kai-Fa-Ban.REV2.0
- 本产品教程与注亍NIOS Ⅱ嵌入式开収,主要由C诧言开収,因此,打好C诧言的基础很重要,在此推荐一本《C程序设计诧言》(第2版),英文名为《The C Programming Language》(Second Edition),该书是由C诧言的设计者Brian W.Kernighan和Dennis M.Ritchie编写的一部介绍标准C诧言及其程序设计方法的权威性经典著作。全面、系统地讱述了C诧言的各个特性及程序设计的基本方法，包括基本概念，类型和表达式、控制流、函数不程序结构、指针不数组、结构
m
- m序列产生器，verilog语言实现,在FPGA上试验过-m code maker
FPGA-M-sequence-generator
- FPGA VHDL 语言M序列发生器，可以帮助各位需要的朋友探讨研究-FPGA VHDL language M-sequence generator, can you help a friend in need of research
cod-m
- flexible viterbi decoder using fpga
m-Sequence
- FPGA,verilog,输出M序列，已调试成功，可直接在Quartus上打开。-FPGA, verilog, output M sequence, has been successfully debugged, can be opened directly on the Quartus.
fpga代码
- 实现了m序列产生，同步信号提取功能，实现了所有功能(The m sequence is generated and the synchronous signal extraction function is realized)
m_sequence
- 基于fpga verilog语言生成的m序列。(Generating m sequences based on FPGA)
m-test
- 产生小m序列，用于扩频系统中，仿真测试正确，反馈级数为4(Generating m sequences)
programme stabilite
- fbdhtg gfngnhgf j mn nmj,m vgvcx